Embodiments of the inventive concept relate to semiconductor memory devices, and more particularly, to semiconductor memory devices using address mapping techniques capable of increasing the efficiency of merge operations. Embodiments of the inventive concept also relate to data write methods performed in semiconductor memory devices using such address mapping techniques. Still other embodiments of the inventive concept relate to user devices that incorporate such semiconductor memory devices and/or data write methods.
Semiconductor memory devices may be characterized in their operative nature as volatile and non-volatile. Volatile memory devices generally perform read/write operations at high speed, but lose stored data in the absence of applied power. In contrast, non-volatile memory devices retain stored data in the absence of applied power. Accordingly, non-volatile memory devices are used to store data that must be retained regardless of power conditions. In particular, among the broad class of non-volatile memory devices, so-called flash memory devices are characterized by high memory cell integration density as compared with other types of EEPROMs. Thus, flash memory devices have proven particularly useful when incorporated into user devices and systems requiring mass data storage (e.g., use as auxiliary memory devices).
Contemporary flash memory devices operate in accordance with a defined erase unit (i.e., a data block size erased during an erase operation) and a defined write unit (i.e., a data block size written or programmed to during a write or program operation). A difference in block size between the erase unit and write unit generally necessitates the use of a specialized software tool commonly referred to as a flash translation layer or FTL.
The FTL is essentially an address mapping scheme that converts a given address (e.g., a logical address) defined in one domain into a corresponding address (e.g., a physical address) defined in another domain. Thus, in common use the FTL translates address types across domain boundaries. For example, a logical address (LA) defined by a host (e.g., a controller, processor, or high level application) may be converted back-and-forth with a corresponding physical address (PA) defined by an arrangement of memory cells in a flash memory device. Hence, the FTL converts respective, yet corresponding, addresses between a host domain and a flash memory device domain.
Address mapping may be accomplished using page mapping, block mapping, or hybrid mapping. A page mapping table is used for page mapping. That is, a page mapping table may be used to perform a mapping operation on a page by page basis between logical page addresses and corresponding physical page addresses.
A block mapping table is used for block mapping. That is, the block mapping table may be used to perform a mapping operation on a block by block between logical block addresses and corresponding physical block addresses.
Hybrid mapping methods essentially use both page mapping and block mapping techniques.
A memory block typically includes multiple pages. The size of a mapping table used for page mapping is therefore tens or hundreds of times larger than an analogous mapping table used for block mapping. Thus, a page mapping table will require a great deal more memory space than a block mapping table.
However, a memory block is rather large and constituent page locations within each block are fixed, despite frequent updates to the pages. For this reason, block mapping necessitates the use of many merge operations to ensure sufficient availability of memory space.